// 带寄存器配置总线的DUT：bus_dut.sv
module bus_dut(
    input                   clk,
    input                   rst_n,
    input                   bus_cmd_valid,
    input                   bus_op,
    input       [15:0]      bus_addr,
    input       [15:0]      bus_wdata,
    input       [7:0]       rx_d,
    input                   rx_dv,

    output reg  [15:0]      bus_rdata,
    output reg  [7:0]       tx_d,
    output reg              tx_en
);

    reg invert;

    always @ (posedge clk) begin
        if (!rst_n) begin
            tx_d <= 8'b0;
            tx_en <= 1'b0;
        end
        else if (invert) begin
            tx_d <= ~rx_d;
            tx_en <= rx_dv;
        end
        else begin
            tx_d <= rx_d;
            tx_en <= rx_dv;
        end
    end

    always @ (posedge clk) begin
        if (!rst_n) begin
            invert <= 1'b0;
        end
        else if (bus_cmd_valid && bus_op) begin
            case(bus_addr)
                16'h9: begin
                    invert <= bus_wdata[0];
                end
                default:begin
                end
            endcase
        end
    end

    always @ (posedge clk) begin
        if (!rst_n) begin
            bus_rdata <= 16'b0;
        end
        else if (bus_cmd_valid && !bus_op) begin
            case(bus_addr)
                16'h9: begin
                    bus_rdata <= {15'b0, invert};
                end
                default: begin
                    bus_rdata <= 16'b0;
                end
            endcase
        end
    end

endmodule